单击此处编辑母版标题样式,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,*,*,Chapter 6,Combinational Logic Design Practices(,组合逻辑设计实践,),Documentation Standard and Circuit Timing(,文档标准和电路定时,),Commonly Used MSI Combinational Logic Device(,常用的中规模组合逻辑器件,),Digital Logic Design and Application,(,数字逻辑设计及应用,),1,Chapter 6 Combinational Logi,Review of Last Class(,内,容回顾,),6.1 Documentation Standard,(,文档标准,),Signal Name and Active Level,(,信号名和有效电平,),Bubble-to-Bubble Logic Design,(,“圈到圈”逻辑设计,),Digital Logic Design and Application,(,数字逻辑设计及应用,),2,Review of Last Class(内容回顾)6.1,6.2,Circuit Timing(,电路定时,),Propagation Delay(,传播延迟,),Timing Analysis(,定时分析,),Timing Diagram(,定时图,),Review of Last Class(,内,容回顾,),Digital Logic Design and Application,(,数字逻辑设计及应用,),3,6.2 Circuit Timing(电路定时)Revie,A B F,0 0 0,0 1 0,1 0 0,1 1 1,A,B,F,开关状态,：1,闭合、0断开,灯的状态：1亮,、0不亮,逻辑与：当且仅当所有输入条件都有效时，输出状态才有效。,开关状态：0闭合、1断开,灯的状态：0亮 、1不亮,A B F,0 0 0,0 1 1,1 0 1,1 1 1,A,B,F,A,B,F,F=A+B,=(A B),Review of Last Class(,内,容回顾,),Digital Logic Design and Application,(,数字逻辑设计及应用,),4,A B FABF开关状态：1闭合、0断开逻辑与,开关的有效状态,：,闭合,灯的有效状态：亮,A,B,F,有反相圈的引脚,表示低电平有效,给定逻辑功能只在符号框的内部发生,Review of Last Class(,内,容回顾,),Digital Logic Design and Application,(,数字逻辑设计及应用,),5,开关的有效状态：闭合ABF有反相圈的引脚给定逻辑功能只在符号,Decoders(,译码器,),Encoders(,编码器,),Multiplexers,(,多路复用器,),Parity Circuits,(,奇偶校验,),Comparators(,比较器,),Adders(,加法器,),Commonly Used MSI Combinational Logic Device(,常用中规模组合逻辑器件）,Enable,Inputs,(,使能输入,),(,输入,编码,),(,输出,编码,),Map,映射,Input,Code,Word,Output,Code Word,Digital Logic Design and Application,(,数字逻辑设计及应用,),6,Decoders(译码器)Commonly Used MS,6.4 Decoder（译码器）,Binary Decoder,(,二进制译码器,),使能,输入,编码,输出,编码,映射,n,位二进制码,2,n,中取1码,2-4译码器,Y0,Y1,Y2,Y3,I0,I1,EN,Yi=EN m,i,0 X X 0 0 0 0,1 0 0 0 0 0,1,1 0 1 0 0,1,0,1 1 0 0,1,0 0,1 1 1,1,0 0 0,输 入,EN I1 I0,输 出,Y3 Y2 Y1 Y0,2-4二进制译码器真值表,当使能端有效时,Y,i,=m,i,Truth Table for a 2-to-4 Binary Decoder,Digital Logic Design and Application,(,数字逻辑设计及应用,),7,6.4 Decoder（译码器）Binary Decode,The,74,x139 Dual,2-,to-4 Decoder(,双2-4译码器74,x139),74,x139,1 X X 1 1 1 1,0,0 0 1 1 1,0,0,0 1 1 1,0,1,0,1 0 1,0,1 1,0,1 1,0,1 1 1,Inputs,G B A,Outputs,Y3_L Y2_L Y1_L Y,0,_L,(1/2 74x139,双2-4,译码器真值表,),Truth Table for One-half of a 74x139,Dual 2-to-4 Decoder,8,The 74x139 Dual 2-to-4 Decoder,74,x139,EN,Digital Logic Design and Application,(,数字逻辑设计及应用,),9,74x139 ENDigital Logic Desi,低位,高位,Yi=EN,mi,G1,G2A_L,G2B_L,EN,Yi_L=Yi=(EN,mi,),EN=G1 G2A G2B,=G1 G2A_L G2B_L,Y0_L,Y1_L,Y7_L,Y2_L,Y3_L,Y4_L,Y5_L,Y6_L,EN,Digital Logic Design and Application,(,数字逻辑设计及应用,),10,低位Yi=EN miG1G2A_LG2B_LENYi,N0,N1,N2,N3,EN_L,+5V,D0_L,D7_L,D8_L,D15_L,用74,x138,设计,4-16,译码器,思路：,16个输出需要,片74,x138？,Y0,Y7,A,B,C,G1,G2A,G2B,Y0,Y7,A,B,C,G1,G2A,G2B,U1,U2,任何时刻只有一片在工作。,4个输入中，,哪些位控制片选,哪些位控制输入,Cascading Binary Decoders,(,级联二进制译码器）,11,N0N3EN_L+5VD0_LD8_L用74x138设计4-,Consider:How to make a 5-to-32 Decoder,with 3-to-8 Decoder?,(,思考：用74,x138,设计 5,-32,译码器,),How many,74,x138 chips to be used,with 32 outputs?,(32,个输出需要多少片74,x138？),Control that only one chip works in any time,(,控制任何时刻只有一片工作,),Use the Enable Inputs(,利用使能端,),Digital Logic Design and Application,(,数字逻辑设计及应用,),12,Consider:How to make a 5-to-3,Consider:How to make a 5-to-32 Decoder with 3-to-8 Decoder?,(,思考：用74,x138,设计 5,-32,译码器,),Control inputs of three low-order bits of a 5-bit code word,(5,个输入的低3位控制输入,),Control chips of two high-order bits of a 5-bit code word,(5,个输入的高2位控制片选,),Use 2-to-4 Decoder,(,利用 2,-4,译码器,),Figure 6-,3,7,Digital Logic Design and Application,(,数字逻辑设计及应用,),13,Consider:How to make a 5-to-3,补充：用译码器和逻辑门实现逻辑函数,F=,(X,Y,Z),(0,3,6,7),=,(X,Y,Z),(1,2,4,5),对于二进制译码器：,Yi=EN m,i,当使能端有效时，,Yi=m,i,对低电平有效输出：,Yi_L=Yi,当使能端有效时，,Yi_L=m,i,=M,i,A,B,C,G1,G2A,G2B,Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7,74,x138,Digital Logic Design and Application,(,数字逻辑设计及应用,),14,补充：用译码器和逻辑门实现逻辑函数F=(X,Y,Z),用译码器和逻辑门实现逻辑函数,Z,Y,X,A,B,C,G1,G2A,G2B,Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7,74,x138,F,+5V,F=,(X,Y,Z),(0,3,6,7),当使能端有效时,Yi=m,i,Digital Logic Design and Application,(,数字逻辑设计及应用,),15,用译码器和逻辑门实现逻辑函数ZAG1Y074x138F+5V,用译码器和逻辑门实现逻辑函数,Z,Y,X,A,B,C,G1,G2A,G2B,Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7,74,x138,+5V,F,F=,(X,Y,Z),(0,3,6,7),Digital Logic Design and Application,(,数字逻辑设计及应用,),16,用译码器和逻辑门实现逻辑函数ZAG1Y074x138+5VF,=,M,1,M,2,M,4,M,5,=,m,1,m,2,m,4,m,5,F=,(X,Y,Z),(1,2,4,5),Z,Y,X,A,B,C,G1,G2A,G2B,Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7,74,x138,+5V,F,Digital Logic Design and Application,(,数字逻辑设计及应用,),17,=M1 M2 M4 M5=m1 m2,BCD Decoder(二十进制译码器),Inputs:4-bit BCD code,Outputs:1-out-of 10 Code,Y0,Y9,I0,I1,I2,I3,多余的6个状态如何处理？,输出均无效：拒绝“翻译”,作为任意项处理,电路内部结构简单,Digital Logic Design and Application,(,数字逻辑设计及应用,),18,BCD Decoder(二十进制译码器)Inputs:,二-十进制译码器,0 0 0 0,0 0 0 1,0 0 1 0,0 0 1 1,0 1 0 0,0 1 0 1,0 1 1 0,0 1 1 1,1 0 0 0,1 0 0 1,1 0 1 0,1 0 1 1,1 1 0 0,1 1 0 1,1 1 1 0,1 1 1 1,0,1 1 1 1 1 1 1 1 1,1,0,1 1 1 1 1 1 1 1,1 1,0,1 1 1 1 1 1 1,1 1 1,0,1 1 1 1 1 1,1 1 1 1,0,1 1 1 1 1,1 1 1 1 1,0,1 1 1 1,1 1 1 1 1 1,0,1 1 1,1 1 1 1 1 1 1,0,1 1,1 1 1 1 1 1 1 1,0,1,1 1 1 1 1 1 1 1 1,0,1 1 1 1 1 1 1 1 1 1,1 1 1 1 1 1 1 1 1 1,1 1 1 1 1 1 1 1 1 1,1 1 1 1 1 1 1 1 1 1,1 1 1 1 1 1 1 1 1 1,1 1 1 1 1 1 1 1 1 1,I3,I2,I1,I0,0,1,2,3,4,5,6,7,8,9,Y0_L,Y9_L,伪,