Click to edit Master title style,*,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,VHDL,Synthesis&Simulation,(Course Information,),Course information,36,学时,陈颖琪,Tel:34204648,Office Room:,电院楼群,1-505,Internet Resources,Books,?VHDL数字电路设计教程?,Volnei A.Pedroni著，乔庐峰等译,电子工业出版社,?VHDL硬件描述语言与数字逻辑电路设计电子工程师必备知识?,侯伯亨，顾新,?电子设计硬件描述语言VHDL?,Douglas L.Perry，学苑出版社,VHDL Design Representation and Synthesis,Armstrong and Gray,Prentice Hall.,Software Tools,Modelsim,Synplify,ISE,Quartus,Contents,Background,Language,Frame of the VHDL code,Detail of the language,Simulation platform,Basic Models,Synthesis&Simulation Tips,Lab&Homework,Analysis VHDL Code,Design synthesizable Digital Modules,Design Test Platform,Course Score,75%exam,25%Lab&homework,