,按一下以編輯母片,第二層,第三層,第四層,第五層,*,按一下以編輯母片標題樣式,前瞻網路安全處理器及相關,SOC,設計與測試技術研發,Network Security Processor and the Related SOC Design and Test Technologies,Bist for RAm IN Seconds,July,2006,MemoryTestingProblem&Solutions,Problem:memory manufacturing is not perfect,Need testing,diagnosis,andrepair,RAMSES:RAM/Flash fault simulator,TAGS:RAM/Flash testalgorithm(pattern)generator,BRAINS:RAM BIST generator,FAME:memory failureanalyzer,Design,(Layout),Defect,Injection,Faulty Cell,Behavior,Fault,Models,Fault,Models,Test,Algorithms,Built-In,Self-Test,Built-In,Self-Repair,Tester,2,MemoryBIST Automation Flow,BRAINS:,B,IST for,RA,Ms,i,n Seco,n,d,s,BIST,Intermediate,Description,Simulation/Synthesis/P&R Flow,BRAINS,gbrains,Memory,Library,BIST,Templates,BID Constructor,Compiler Kernel,BIST Design,Activation Sequences,Integration Scripts,Memory Spec,Test Requirement,Memory,Compiler,IP,Generators,Command,Scripts,GUI,3,Test Scheduleand Test Grouping,Single-port,SRAM,Group 0,Controller,Sequencer 1,Dual-port,SRAM,Group 1,2,R1W,Register File,Single-port,SRAM,Read port,Write port,Read-write port,Sequencer 0,Group 0,Parameters:,Memorytype,Memoryspec.,Power constraint,User define,4,Algorithm Programming&TestScheduling,5,Driving Capability&PipelineOptimization,6,BIST CircuitGenerationFlow,MemoryInfo.,Test Algorithm,Test Scheduling,Driving/Timing Spec.,BIST Compile,Start,RTL,TB,Syn.Script,Memorymodel,address,word width,Default/Programmable,Auto/Userdefined,Pinloading,latency,BID,7,BISTArchitecture,Memory,BIST,External Tester,MBS,MSI,MBO,MRD,MSO,MBC,MBR,MCK,Controller,RAM,RAM,RAM,RAM,RAM,RAM,Sequencer,Sequencer,Sequencer,TPG,TPG,TPG,TPG,TPG,TPG,8,ExperimentResult&Comparison,MemorySpec:,64X64:2modules,64X128:3modules,512X64:1module,512X128:2modules,Fullspeedtesting-clockrate:100MHz,Diagnosisfunction,Testalgorithm:MarchC-(Mentor),MarchCW(BRAINS),Test time,(cycle),Gate count,BRAINS,2,423,500,28,910,Mentor,20,080,900,30,353,9,FAME,FAME:FailureAnalyzerforMemories,MECA:MemoryErrorCatcherandAnalyzer,RAMSES:RAMfaultsimulator,TAGS:RAMtestalgorithmgenerator,ERA:RAMerroranalyzer,MDD:MemoryDefectDiagnosisTool,AFA:AutomaticFaultAnalyzer,FPA:Failure/FaultPatternAnalyzer,GUI-basedFailure/FaultPatternViewer,10,FAME:,F,ailure,A,nalyzerfor,Me,mory,11,RealisticDefectInjection,Purpose:todetermineifacircuitisdamagedbyacertaindefect,OpenDefects,ShortDefects,D,Contact/Via,MissingContact,D,12,DiagnosticsUsingFaultPatterns,Acause-effectapproach:,Fault,Patterns,Defective,Netlist,Realistic Fault,Patterns,Prediction Stage,Application Stage,Simulation,Reduction,Defect,Dictionary,Defect,Candidates,13,FaultPatternAnalysisResults,14,MemoryDefectDiagnostics(MDD),MemoryDefectDiagnostics,15,Failure/FaultPatternViewer,16,Summary,Fault-patternorientedmethodologyfordefectdiagnostics,Layout-baseddefectinjectionanddefectdictionarycreation,Combinesstrengthsofconventionalfailure-patternapproachandourfault-typeapproach,Integratedmemoryfailureanalysisframework,Cost-effectivedefectidentificationandyieldimprovement,BRAINScreatesBIST circuitfor allmemorycores,Used in early stage of SOCdesign,Memorylibraryprovideseasy accesstodifferentmemory types,17,