单击此处编辑母版标题样式,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,*,VLSI Test:Lecture 1 Introduction,*,VLSI TESTING,超大规模集成电路测试技术,2024/11/19,1,VLSI Test:Lecture 1 Introduction,Teacher,老师,Liu Peng-xia/,刘 蓬 侠,Email/,电子邮箱,:,Tel/,电话,:4575827,Institute of Microelectronics/,微电子所,School of Computer/,计算机学院,National University of Defense Technology/,国防科大,2024/11/19,2,VLSI Test:Lecture 1 Introduction,Background Knowledge,背景知识,Boolean Algebra/,布尔代数,整个电子、通信及计算机领域的数学基础之一,Principles of Electronic Circuits/,电子电路原理,所有与电子设计相关的技术领域的专业基础,Digital Logic Design/,数字逻辑设计,进行大规模芯片和系统设计的技术基础,2024/11/19,3,VLSI Test:Lecture 1 Introduction,Background Knowledge(,cont.),背景知识,（续）,VLSI Design/,超大规模集成电路设计,使你了解实际的设计流程、方法和基本技术，从而更好地理解测试技术的地位和作用,The Science and Engineering of Microelectronic Fabrication/,微电子制造科学原理和工程技术,使你熟悉底层的物理实现技术和工艺，从而更好地理解生产造成的物理缺陷,2024/11/19,4,VLSI Test:Lecture 1 Introduction,Course Plan,(cont.),课程安排,（续）,Time/,时间安排,One or twice a week,for 2 hours,for 7 weeks,Assignments/,作业,about 7,Examination/,考试,written exam in the finals,Grading/,评分,In-class presentation 10%,Assignments 30%,Final examination 60%,2024/11/19,6,VLSI Test:Lecture 1 Introduction,Lecture 1 Introduction,第一讲：概述,Realistic model/,现实模型,Roles of VLSI testing/,角色,Criteria of VLSI testing/,准则,Methods of VLSI testing/,方法,Costs of VLSI testing/,成本,Course outline/,课程大纲,2024/11/19,7,VLSI Test:Lecture 1 Introduction,1 Realistic model,现实模型,考试,Status/,地位,essentiality and importance,Aims/,目标,check and/or filter,Objects/,对象,men and women,Criteria/,准则,eligibility ratio,Contents/,内容,aspects and points,2024/11/19,8,VLSI Test:Lecture 1 Introduction,2 Roles of VLSI testing,角色,Determine requirements,Write specifications,Design synthesis and Verification,Fabrication,Manufacturing test,Chips to customer,Customers need,Test development,2024/11/19,10,VLSI Test:Lecture 1 Introduction,2 Roles of VLSI testing,(Cont.),角色,（续）,-,aims,Detection/,探测,Determination whether or not the,device under test,(DUT)has some fault.,Diagnosis/,诊断,Identification of a specific fault that is present on DUT.,Failure mode analysis(FMA)/,失效模式分析,Determination of manufacturing process errors that may have caused defects on the DUT.,2024/11/19,11,VLSI Test:Lecture 1 Introduction,2 Roles of VLSI testing,(Cont.),角色,（续）,-,Summary,Status/,地位,：,essentiality and importance,Aims/,目标,：,check and/or filter,Objects/,对象,：,manufactured chips,Contents/,内容,：,manufactured defects,Means/,方式,：,ATE,Time/,时间,：,from beginning to the end,Sites/,场地,：,testing room,2024/11/19,13,VLSI Test:Lecture 1 Introduction,3 Criteria of VLSI testing,(Cont.),评价准则,（续）,-,Real Tests,Fault coverage/,故障覆盖率,Problems,Based on analyzable fault models,which may not map on real defects.,Incomplete coverage of modeled faults due to high complexity.,2024/11/19,15,VLSI Test:Lecture 1 Introduction,3 Criteria of VLSI testing,(Cont.),评价准则,（续）,-,Filter Process,Fabricated,chips,Good chips,Defective chips,Prob(good)=y,Prob(bad)=1-y,Prob(pass test)=high,Prob(fail test)=high,Prob(fail test)=low,Prob(pass test)=low,Mostly,good,chips,Mostly,bad,chips,2024/11/19,16,VLSI Test:Lecture 1 Introduction,4 Methods of VLSI testing,(Cont.),方法,（续）,-,special,Structure and function/,结构和功能,Memory test/,存储器,Structure:array,Function:key,Special fault model,Special test procedure,Analog test/,模拟器件,Structure:capacitor,resistor,Function:Infinite signal range,No widely-accepted fault model,2024/11/19,18,VLSI Test:Lecture 1 Introduction,4 Methods of VLSI testing,(Cont.),方法,（续）,-,special,Effect/,效应,Delay test/,路径延迟,连接于初级输入（触发器）和初级输出（触发器）之间的电路为组合电路,Incorrect combinational path-delay,IDDQ test/,静态电流,IDDQ,指,CMOS,管开关行为完成后的静态漏电流,Increased IDDQ,2024/11/19,19,VLSI Test:Lecture 1 Introduction,4 Methods of VLSI testing,(Cont.),方法,（续）,-,Design for Testability(DFT),DFT/,可测试性设计,refers to hardware design styles or added,hardware that reduces test generation complexity.,Example,Test hardware applies tests to blocks A and B and to internal bus;avoids test generation for combined A and B blocks.,Logic,block A,Logic,block B,PI,PO,Test,input,Test,output,Int.,bus,2024/11/19,20,VLSI Test:Lecture 1 Introduction,4 Methods of VLSI testing,(Cont.),方法,（续）,-,Design for Testability(DFT),Scan design/,扫描设计,Idea:Test combinational and sequential logic separately,Method:Link flip-flops to scan chain,BIST/,内建自测试,Idea:Test itself,Method:Add logics for generating test patterns and analyzing results,2024/11/19,21,VLSI Test:Lecture 1 Introduction,4 Methods of VLSI testing,(Cont.),方法,（续）,-,Design for Testability(DFT),Boundary scan/,边界扫描,Idea:Test chips separately,Method:Link I/O of chip to scan chain(JTAG,1194.1),Analog test bus/,模拟测试总线,Idea:Provide access to selected nodes for testing,Method:ATB(IEEE Standard 1194.4),2024/11/19,22,VLSI Test:Lecture 1 Introduction,6 Course Outline,课程大纲,-,Part I:Introduction,Basic concepts and definitions,基本概念和定义,Test process and ATE,测试过程和设备,Test economics and product quality,测试经济和产品质量,Fault modeling,故障模型,2024/11/19,24,VLSI Test:Lecture 1 Introduction,6 Course Outline,(Cont.),课程大纲,（续）,-,Part II:Test Methods,Logic and fault