Click to edit Master title style,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,*,VHDL,Simulation&Synthesis,Agenda,Other Features in VHDL,Generate,Assert,Function Overloading,FILE IO,Generate Example(1),ram32:,ram_0:static_ram,port,map,(cs_b,we_b,oe_b,abus(7 downto 0),dbus(7 downto 0);,ram_1:static_ram,port,map,(cs_b,we_b,oe_b,abus(7 downto 0),dbus(15 downto 8);,ram_2:static_ram,port,map,(cs_b,we_b,oe_b,abus(7 downto 0),dbus(23 downto 16);,ram_3:static_ram,port,map,(cs_b,we_b,oe_b,abus(7 downto 0),dbus(31 downto 24);,end,generate,ram32;,RAM0,RAM1,RAM2,RAM3,8-bit,Bus,8-bit,Bus,8-bit,Bus,8-bit,Bus,32-bit,Bus,8-bit addr,8-bit addr,8-bit addr,8-bit addr,Generate Example(2),ram32:,for,i,in,3 downto 0,generate,ram:,static_ram,port,map,(cs_b,we_b,oe_b,abus(7 downto 0),dbus(8*i+7 downto 8*i);,end,generate,ram32;,RAM0,RAM1,RAM2,RAM3,8-bit,Bus,8-bit,Bus,8-bit,Bus,8-bit,Bus,32-bit,Bus,8-bit addr,8-bit addr,8-bit addr,8-bit addr,Generate,Label,:,for,ParameterName,in,Range,generate,ConcurrentStatements.,end,generate,Label,;,Label,:,if,Condition,generate,ConcurrentStatements.,end,generate,Label,;,Generate Example(3),Adder,a(0)a(1)a(2)a(wid-1),b(0)b(1)b(2)b(wid-1),sum(0)sum(1)sum(2)sum(wid-1),carry,HA,FA,FA,FA,a(0),b(0),c_in(1),a(1),b(1),c_in(2),a(2),b(2),c_in(3),c_in(win-1),a(wid-1),b(wid-1),sum(0),sum(1),sum(2),sum(wid-1),carry,Generate Example(4),adder:,for,i,in,0,to,wid-1,generate,ls_bit:,if,i=0,generate,ls_cell:HA,port map,(a(0),b(0),sum(0),c_in(1);,end,generate,lsbit;,middle_bit:,if,i 0,and,i wid-1,generate,middle_cell:FA,port,map,(a(i),b(i),c_in(i),sum(i),c_in(i+1);,end,generate,middle_bit;,ms_bit:,if,i=wid-1,generate,ms_cell:FA,port,map,(a(i),b(i),c_in(i),sum(i),carry);,end,generate,ms_bit;,end,generate,adder;,HA,FA,FA,FA,a(0),b(0),c_in(1),a(1),b(1),c_in(2),a(2),b(2),c_in(3),c_in(win-1),a(wid-1),b(wid-1),sum(0),sum(1),sum(2),sum(wid-1),carry,Agenda,Generate,Assert,Function Overloading,FILE IO,Assert,Definition,Label:assert Condition,report StringExpression,severity Expression;,Note,The message is written when the Condition is False!,The default string for report clause is“Assertion violation,The default string for severity clause is“ERROR,Concurrent Assertions&Concurrent Procedure Calls,Label:,assert,condition,report,error_string,severity,severity_value,;,Label:,process,begin,assert,condition,report,error_string,severity,severity_value,;,wait,sensitivity_clause,;,end,process,Label;,concurrent assertions,concurrent procedure calls,Assert Example(1),assert,not(Reset=0 and Set=0),report,R-S conflict,severity,Failure,;,Assert Example(2),Severity_level,type,severity_level,is,(,note,warning,error,failure,);,(In standard.vhd),Agenda,Generate,Assert,Function Overloading,FILE IO,Function Overloading,VHDL allows two subprograms to have the,same name,provided the,number or base types of parameters differs,Function Overloading(Example 1),function,Foo,(value:,bit,)return boolean;,function,Foo,(value:,std_logic,)return boolean;,Function Overloading(Example 2),function,+,(,arg1,arg2:STD_LOGIC_VECTOR,),return,STD_LOGIC_VECTOR,;,function,+,(,L,R:UNSIGNED,)return,UNSIGNED;,function,+,(,L,R:SIGNED,)return,SIGNED;,Function Overloading(Example 3),FUNCTION+(arg1,arg2:STD_LOGIC_VECTOR)RETURN STD_LOGIC_VECTOR IS,CONSTANT ml :INTEGER:=maximum(arg1length,arg2length);,VARIABLE lt :STD_LOGIC_VECTOR(1 TO ml);,VARIABLE rt :STD_LOGIC_VECTOR(1 TO ml);,VARIABLE res :STD_LOGIC_VECTOR(1 TO ml);,VARIABLE carry :STD_LOGIC:=0;,VARIABLE a,b,s1:STD_LOGIC;,-Unsigned arithmetic addition of two vectors.MSB is Left.,ATTRIBUTE synthesis_return OF res:VARIABLE IS ADD;,BEGIN,lt:=zxt(arg1,ml);,rt:=zxt(arg2,ml);,FOR i IN resreverse_range LOOP,a:=lt(i);,b:=rt(i);,s1:=a+b;,res(i):=s1+carry;,carry:=(a AND b)OR(s1 AND carry);,END LOOP;,RETURN res;,END;,FUNCTION+(arg1,arg2:UNSIGNED)RETURN UNSIGNED IS,CONSTANT ml :INTEGER:=maximum(arg1length,arg2length);,VARIABLE lt :UNSIGNED(1 TO ml);,VARIABLE rt :UNSIGNED(1 TO ml);,VARIABLE res :UNSIGNED(1 TO ml);,VARIABLE carry :STD_LOGIC:=0;,VARIABLE a,b,s1:STD_LOGIC;,-Unsigned arithmetic addition of two vectors.MSB is Left.,ATTRIBUTE synthesis_return OF res:VARIABLE IS ADD;,BEGIN,lt:=zxt(arg1,ml);,rt:=zxt(arg2,ml);,FOR i IN resreverse_range LOOP,a:=lt(i);,b:=rt(i);,s1:=a+b;,res(i):=s1+carry;,carry:=(a AND b)OR(s1 AND carry);,END LOOP;,RETURN res;,END;,Function Overloading(Example 4),function,+,(a,b:byte),return,byte is,begin,return,int_to_byte(byte_to_int(a)+byte_to_int(b);,end,+;,X1000_0010,+,X0000_FFD0,+,(X1000_0010,X0000_FFD0),Agenda,Generate,Assert,Function Overloading,FILE IO,Text File,Binary File,Read/Write Text File,Awfe,011100010,-,Disk File,1001011011,Line variable,ReadLine(),Read(),Data,Object,Awfe,011100010,-,Disk File,1001011011,Line variable,WriteLine(),Write(),Data,Object,Read From Text File,Write To Text File,Read/Write Text File Steps,Step 1Define user data object,DataObj,Step 2Define,Line,object,LineObj,variable,LineObj,:line;,Step 2Define,TextFile,object,FileObj,file,FileObjec